Design Compiler Optimization: A Hierarchical Approach

The sources detail the optimization flow within Synopsys Design Compiler, outlining a three-tiered process that transforms a high-level design description into a technology-specific, gate-level implementation. This hierarchical approach ensures a balance between design goals, design rules, and the inherent limitations of the target technology.

The Optimization Flow:

Design Compiler's optimization flow comprises several interconnected steps, each contributing to the overall goal of producing an efficient and functional circuit. Figure 85 in source visually represents this flow, highlighting:

• Automatic Ungrouping: This initial step may automatically merge subdesigns into their parent cells to improve timing and area efficiency. You can control this behavior, manually ungrouping hierarchies, or preventing it altogether.
• High-Level Optimization: At this stage, resource allocation and sharing, arithmetic optimizations, and potentially advanced datapath transformations are applied to the design.
• Multiplexer Mapping and Optimization: Design Compiler identifies and optimizes multiplexer structures, generating efficient MUX trees based on design constraints.
• Sequential Mapping: The design's sequential elements are mapped to technology-specific gates, aiming to meet timing and area goals.
• Structuring and Mapping: Unmapped logic is optimized and mapped to technology gates, often introducing intermediate variables to improve area efficiency.
• Automatic Uniquification: This step addresses potential issues related to multiply-driven nets, ensuring proper signal propagation and avoiding unintended logic behavior.
• Implementing Synthetic Parts: Abstract representations of complex logic functions (synthetic modules) are converted into concrete architectural implementations.
• Timing-Driven Combinational Optimization: Design Compiler fine-tunes the combinational logic, restructuring critical paths and exploring alternative implementations to enhance timing performance.
• Register Retiming: The positions of registers and latches within the design are adjusted to improve timing, potentially reducing the number of registers needed while still meeting performance targets.
• Delay and Leakage Optimization: Design Compiler strives to minimize both delay and leakage power consumption, targeting non-critical paths for power reduction without compromising timing.
• Design Rule Fixing: The final netlist is checked and corrected to ensure strict adherence to the technology library's design rules, guaranteeing manufacturability and functional correctness.
• Area Optimization: Design Compiler attempts to further reduce the circuit's area without impacting timing performance, often by employing logic restructuring and gate-level optimizations.

Optimization Levels:

Within this flow, Design Compiler implements optimization at three distinct levels, each focusing on a specific aspect of the design:

1. Architectural Optimization

• Scope: Operates on the high-level HDL description of the design.
• Goal: Transforms the design's structure to achieve an efficient architecture before mapping to specific gates.
• Techniques:
  • Sharing common subexpressions: Reduces redundancy by identifying and reusing identical logic blocks.
  • Resource sharing: Minimizes hardware utilization by employing a single component for multiple, non-concurrent operations.
  • DesignWare implementation selection: Chooses optimized implementations from DesignWare libraries to implement complex functions efficiently (not available in DC Expert).
• Impact: Significantly influences the overall area and performance of the final circuit, setting the stage for subsequent optimization levels.
• Coding Style Influence: The way the HDL code is written greatly affects architectural optimization.

2. Logic-Level Optimization

• Scope: Works on the generic technology (GTECH) netlist, a technology-independent representation of the design.
• Goal: Manipulates the logic structure to further refine the circuit before mapping to specific library gates.
• Techniques:
  • Structuring: Adds intermediate variables and logic structure to potentially reduce area, particularly beneficial for non-critical paths.
  • Flattening: Removes levels of hierarchy to enable greater optimization freedom, potentially leading to improved area and timing, but at the cost of increased runtime and memory usage.
• Impact: Further refines the circuit's logic, often leading to more compact and efficient implementations.

3. Gate-Level Optimization

• Scope: Operates on the technology-specific netlist generated after mapping to the target library gates.
• Goal: Performs final-stage optimizations on the mapped netlist to meet timing, power, and area constraints.
• Techniques:
  • Mapping: Selects specific gates from the target libraries to implement the design's logic functions, aiming to balance timing, area, and power requirements.
  • Delay optimization: Focuses on reducing critical path delays to meet performance targets, employing techniques like gate sizing, buffer insertion, and path restructuring.
  • Power optimization: Aims to minimize power consumption, often utilizing multi-threshold voltage libraries and targeting non-critical paths for power reduction.
  • Design rule fixing: Ensures the netlist strictly adheres to all design rules defined in the technology library, guaranteeing manufacturability and functional correctness.
  • Area recovery: Attempts to reduce the circuit's area without negatively affecting timing performance, often employing logic restructuring and gate-level optimizations.
• Impact: Fine-tunes the circuit's implementation using library-specific techniques, achieving the final balance between design goals and technology limitations.

Table Summarizing Optimization Levels

Feature	Architectural Optimization	Logic-Level Optimization	Gate-Level Optimization
Design Stage	High-level HDL description	Generic technology (GTECH) netlist	Technology-specific, mapped netlist
Goal	Efficient design architecture	Refined logic structure	Optimized gate-level implementation
Techniques	Subexpression sharing, resource sharing, DesignWare	Structuring, flattening	Mapping, delay optimization, power optimization, design rule fixing, area recovery
Impact	Major influence on overall area and performance	Further refinement of circuit logic	Final-stage optimization to meet timing, power, and area goals while adhering to design rules
Design Compiler	Performed by both compile and compile_ultra	Performed by both compile and compile_ultra	Performed by both compile and compile_ultra, with additional features and control provided by compile_ultra and specialized commands

By understanding the different optimization levels and how they interact, designers can effectively leverage Design Compiler's capabilities to create high-quality circuits that meet both functional and performance requirements.